1. Field of the Invention
The present invention relates to a method for forming a magnetic layer of magnetic random access memory (MRAM) and more particularly to a method that effectively prevents quality of magnetic layer is degraded by uneven underlying layer.
2. Description of the Prior Art
A magnetic memory element has a structure that includes ferromagnetic layers separated by a non-magnetic layer. Information is stored as directions of magnetization vectors in magnetic layers. Magnetic vectors in one magnetic layer, for instance, are magnetically fixed or pinned, while the magnetization direction of the other magnetic layer is free to switch between the same and opposite directions as information which are called "Parallel" and "Anti-parallel" states, respectively. In response to Parallel and Anti-parallel states, the magnetic memory element represents two different resistances. The resistance indicates minimum and maximum values when the magnetization vectors of two magnetic layers point in substantially the same and opposite directions, respectively. Accordingly, a detection of changes in resistance allows an MRAM device to provide information stored in the magnetic memory element.
An MRAM devices integrates magnetic memory elements and other circuits, for example, a control circuit for magnetic memory elements, comparators for detecting states in a magnetic memory element, input/output circuits, etc. There circuits usually are fabricated in the process of complementary metal-oxide semiconductor (CMOS) technology in order to lower the power consumption of the MRAM device.
In addition, a magnetic memory element includes some very thin layers, some of them are about tens of angstroms thick. The performance of the magnetic memory element is sensitive to the surface conditions on which magnetic layers are deposited. Accordingly, it is necessary to make a flat surface to prevent the characteristics of an MRAM device (or magnetic layer) from degrading.
In conventional structure of MRAM, magnetic layer 10 usually is located on dielectric layer 11 that covers substrate where some metal structures 13 locates on, as FIG. 1A shows. However, owing to limitation of practical fabrication, it is usually unavoidable that some voids 14 exist inside dielectric 11 layer. Therefore, voids 14 maybe exposed after sequentially chemical mechanical polish process when location of voids is closed to surface of dielectric layer 11, and then quality of magnetic layer 10 is possibly stochastically degraded for surface of dielectric layer 11 possibly is not flat, refers to FIG. 1B. Moreover, size of voids 14 is increased and distance between voids 14 and surface of dielectric layer 11 is decreased whenever aspect ratio is increased by stop layer 15, as shown in FIG. 1C. Certainly, defect of voids 14 can be effectively prevent by application of dielectric layer 11 which with high gap fill ability. However, quality of magnetic layer 10 stronger relies on flat of surface of underlying dielectric layer 11, but surface of dielectric layer 11 maybe not flat when dielectric layer 11 is sensitive to substrate 12 (or stop layer 15) and then structure of dielectric layer 11 is porous, as FIG. 1D shows. Though dielectric layer 11 with high gap fill ability possibly replaces voids 14 by porous structure, and then quality of magnetic layer 10 still is degraded. For example, when stop layer 15 is silicon nitride layer and dielectric layer 11 is high O3 tetraethyl-orthosilicate SiO2 layer, high gap fill ability of high O3 tetraethyl-orthosilicate SiO2 layer can reduces formation of voids 14 but structure of high O3 tetraethyl-orthosilicate SiO2 layer also is porous. In addition, formation of voids can be effectively prevented by application of high density plasma. However, cost of high density plasma is large and then application of high density plasma is limited.
Correspondingly, quality of magnetic layer is important for magnetic random access memory and then how to provide a flat underlying layer for formation of magnetic layer is a needle technology in contemporary semiconductor field.